This invention relates to a process for forming an integrated circuit structure, and more particularly, to a process for forming a self-aligned, oxide isolated, walled emitter integrated circuit structure.
The advantages of an oxide isolated bipolar integrated circuit structure are well recognized, and include, in particular, increased circuit operating speed and increased packing density. In this structure iolation between adjacent devices is provided by an isolation oxide which extends through the epitaxial layer to the underlying substrate. Devices are thus isolated on the edge by the oxide and on the bottom by the PN junction between the epitaxial layer and the substrate. Still further increases in speed and density can be achieved with a walled emitter structure, that is, a structure in which the emitter region terminates at the oxide isolation. To fully realize the optimum in packing density, device contact areas must be self-aligned since otherwise valuable space must be expended to provide for possible misalignment tolerances.
While the advantages of oxide isolated, walled emitter structures have been recognized, available processes have heretofore been inadequate for reliably producing such structures. Some prior art process have led to low yields primarily due to emitter-to-collector leakage and/or shorting. This results from the particular diffusion profile adjacent the oxide isolation, and specifically results from the well known "breaking" which occurs in processes which employ localized oxidation. To overcome such yield limitations, other prior art structures have resorted to epitaxial bases or the like which sacrifice a major portion of the performance and density benefit sought.
Accordingly, it is an object of this invention to provide a process for fabricating high yielding, oxide isolated, walled emitter device structures.
It is a further object of this invention to provide a process for fabricating high density, potentially high speed, self-aligned integrated circuit structures.
It is a still further object of this invention to provide a process for fabricating high speed integrated circuit structures wherein device current gain and base series resistance can be independently controlled.